1. Technical Field
The present invention relates to a phase locked loop, and more particularly, to a phase locked loop used with a clock tree of a field programmable gate array (FPGA).
2. Background Art
Conventional phase locked loops have been developed by the electronics industry to provide precise phase and frequency locking in various applications in which precise timing of clock signals is required. An example of a typical application in which a conventional phase locked loop can be implemented to provide precise phase and frequency locking of clock signals is a conventional matrix clock tree in an FPGA with interconnect encoding. An example of a conventional FPGA with interconnect encoding is described in U.S. Pat. No. 5,723,984, incorporated herein by reference, assigned to Advanced Micro Devices, Inc., the assignee of the present invention.
FIG. 1 shows a block diagram of a conventional phase locked loop which typically includes a phase/frequency detector 2, a charge pump 4, a loop filter 6, and a voltage controlled oscillator 8 which generates a phase locked loop output signal PLL.sub.-- OUT at a frequency F.sub.out. The phase/frequency detector 2 compares the phase and frequency of an input clock signal CLK with those of a feedback signal FB and in response generates phase/frequency correction signals for the charge pump 4. The phase/frequency correction signals comprise an up signal and a down signal transmitted on two separate signal paths. The up and down signals depend upon the relationship of the phase of the feedback signal FB to the input clock signal CLK. For example, when the input clock signal CLK and the feedback signal FB are in a perfect phase lock, the up and down signals generated by the phase/frequency detector 2 have perfectly matched pulses with an equal pulse width, as shown in FIG. 2A.
FIG. 2B shows the pulses of the up and down signals when an upshifting of the phase locked loop output signal PLL.sub.-- OUT is required to enable the feedback signal FB to be phase locked with the input clock signal CLK. In this case, the pulse width of the up signal is greater than that of the down signal. The leading edges of the corresponding pulses of the up and down signals are timed to coincide with each other, whereas the trailing edges of the up signal pulses lag behind those of the corresponding down signal pulses.
FIG. 2C shows the up and down signal pulses when a downshifting of the phase locked loop output signal PLL.sub.-- OUT is required to enable the feedback signal FB to be phase locked with the input clock signal CLK. In this situation, the pulse width of the down signal is greater than that of the up signal. The leading edges of the corresponding pulses of the up and down signals are timed to coincide with each other, whereas the trailing edges of the down signal pulses lag behind those of the corresponding up signal pulses.
Referring back to FIG. 1, the charge pump 4 generates a pump current I.sub.c in response to receiving the up and down signals from the phase/frequency detector 2. The charge pump 4 detects a difference between the pulse width of the up and down signals generated by the phase/frequency detector 2 and adjusts the pump current I.sub.c if the pulses of the up and down signals do not match each other. For example, when the input clock signal CLK and the feedback signal FB are in a perfect phase lock and the up and down signal pulses are perfectly matched as shown in FIG. 2A, no phase or frequency shift in the output signal PLL.sub.-- OUT is required, and therefore no change in the pump current I.sub.c is required.
In the case in which the phase/frequency detector 2 outputs up and down signal pulses as shown in FIG. 2B, the charge pump 4 determines that the pulse width of the up signal is greater than that of the down signal and in response adjusts the pump current I.sub.c upward to increase the frequency F.sub.out of the output signal PLL.sub.-- OUT, such that the frequency of the feedback signal FB is increased to achieve a phase lock with the input clock signal CLK. In the case in which the phase/frequency detector 2 outputs up and down signal pulses as shown in FIG. 2C, the charge pump 4 determines that the pulse width of the down signal is greater than that of the up signal and in response adjusts the pump current I.sub.c downward to decrease the frequency of the output signal PLL.sub.-- OUT in order to achieve a phase lock between the signals CLK and FB.
The loop filter 6 in FIG. 1 may be either a conventional passive loop filter or a conventional active loop filter which filters out undesirable noises and high frequency jitters in the pump current signal I.sub.c generated by the charge pump 4. The loop filter may be a conventional resistor-capacitor (RC) low pass filter well known to a person skilled in the art.
The loop filter 6 outputs a control voltage V.sub.c to the voltage controlled oscillator 8, which in response generates a phase locked loop output signal PLL.sub.-- OUT having an output frequency F.sub.out. The output frequency F.sub.out generated by the voltage controlled oscillator 8 is dependent upon the control voltage V.sub.c. In a feedback loop 10, the conventional phase locked loop may include a frequency divider 12 which divides the output frequency F.sub.out of the phase locked loop by a predetermined divisor to generate the feedback signal FB. The divisor, that is, the ratio of the frequency F.sub.out of the phase locked loop output signal PLL.sub.-- OUT to the frequency of the feedback signal FB, is determined by the desired frequency F.sub.out of the output signal PLL.sub.-- OUT relative to the frequency of the input clock signal CLK. If the frequency of the output signal PLL.sub.-- OUT is desired to be the same as that of the input clock signal CLK, then the frequency divider need not be provided in the feedback loop 10.
The phase locked loop output signal PLL.sub.-- OUT may be provided as a timing signal to a conventional matrix clock tree 14, such as the one for distributing a clock signal to a plurality of configurable logic blocks (CLBs) in an FPGA, as described in U.S. patent application Ser. No 09/199,664, entitled "A Clock Tree Topology" filed Nov. 25, 1998, by Bradley Sharpe-Geisler, incorporated herein by reference. The phase-locked loop output PLL.sub.-- OUT generated by the conventional phase locked loop as shown in FIG. 1 may also be provided as a clock signal for many other applications known to a person skilled in the art.
When the input clock signal CLK is initially provided to the phase/frequency detector 2 in the conventional phase locked loop as shown in FIG. 1, the control voltage V.sub.c from the loop filter 6 may take a finite time before it settles to a steady-state voltage level to achieve a phase lock. A typical curve of the loop filter control voltage vs. time (V.sub.c vs. t) is illustrated in FIG. 3, which shows the magnitude of the loop filter control voltage V.sub.c from the time of starting the input clock signal CLK to the time of achieving a steady-state voltage V.sub.c ' at point C. Prior to achieving a steady state at point C, the loop filter control voltage V.sub.c, which controls the frequency F.sub.out of the phase locked loop output signal PLL.sub.-- OUT, may swing upward and downward due to relatively large variations in the up and down signals from the phase/frequency detector 2 shortly after the phase locking operation is initiated.
The voltage swing in V.sub.c during a transient state prior to achieving the steady state may cause the conventional phase locked loop as shown in FIG. 1 to achieve a false phase lock when it is still in the transient state. For example, the curve (V.sub.c vs. t) as shown in FIG. 3 crosses the steady state loop filter voltage V.sub.c ' at points A and B prior to achieving the "true" steady state at point C. When the voltage V.sub.c ' is applied to the voltage controlled oscillator 8 in FIG. 1, the phase locked loop output signal PLL.sub.-- OUT is at the desired phase locked frequency. However, when the loop filter voltage V.sub.c crosses the voltage level V.sub.c ' at points A and B during the voltage swing prior to achieving the steady state, a "false" phase lock may occur at either point A or B.
In order to avoid data errors which may occur due to a false lock from a phase locked loop in a circuit, such as an FPGA, fixed time delays have been provided after clock start. However, a fixed time delay does not ensure a true phase lock because the duration of the transient state prior to achieving the steady state may not be the same for each phase locking operation. A very long delay to assure that false locks do not occur is also undesirable due to fast circuit start up time requirements for many circuits.
Because the conventional phase locked loop as shown in FIG. 1 is unable to differentiate between a false phase lock at point A or B and a true phase lock at point C on the curve (V.sub.c vs. t), there is a need for a phase locked loop that is able to determine that a true phase lock is achieved when the loop filter control voltage V.sub.c is in a steady state.